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“With the addition of a whole new line of high density SSDs that is both performance- and value-driven, we believe the 3-bit V-NAND will accelerate the transition of data storage devices from hard disk drives to SSDs,” said Jaesoo Han, Senior Vice President, Memory Sales & Marketing, Samsung Electronics. “The wider variety of SSDs will increase our product competitiveness as we further expand our rapidly growing SSD business.”
The 3-bit V-NAND is Samsung’s latest second generation V-NAND device, which utilizes 32 vertically stacked cell layers per NAND memory chip. Each chip provides 128 gigabits (Gb) of memory storage. In Samsung’s V-NAND chip structure, each cell is electrically connected to a non-conductive layer using charge trap flash (CTF) technology. Each cell array is vertically stacked on top of one another to form multibillion-cell chips. The use of 3 bit-per-cell, 32-layer vertically stacked cell arrays sharply raises the efficiency of memory production. Compared to Samsung’s 10 nanometer-class* 3-bit planar NAND flash, the new 3-bit V-NAND has more than doubled wafer productivity.
Samsung introduced its first generation V-NAND (24 layer cells) in August 2013, and introduced its second generation V-NAND (32-layer) cell array structure in May 2014. With the launch of the 32-layer, 3-bit V-NAND, Samsung is leading the 3D memory era by speeding up the evolution of V-NAND production technology. After having first produced SSDs based on 3-bit planar NAND flash in 2012, Samsung has proven that there is indeed a mass market for high-density 3-bit NAND SSDs.
The industry’s first 3-bit 3D V-NAND will considerably expand market adoption of V-NAND memory, to SSDs suitable for general PC users, in addition to efficiently addressing the high-endurance storage needs of most servers today.
